This invention relates to clock deskewing techniques used in synchronous electronic systems. In a synchronous electronic system, a master clock is normally provided which is used to synchronize the different components of the system requiring timed operation. In typical systems of this type, the master clock experiences delays along the distribution network, which results in loss of clock margin and potential errors. In the past, the normal solution employed to address this variable delay problem has been to slow down the master clock to accommodate delay variations. This solution suffers from the disadvantage that the entire system operation is prolonged, which slows down the processing time or operational time of the associated system circuits.
In order to attempt to provide a more suitable solution to the problem of variable clock delays, several techniques have been employed. One such technique employs a structured set of design rules in arranging the circuit components and clock path lengths to minimize delay variations from the clock source to the various load destinations. Another technique employed in the past provides a plurality of phase lock loops or delay line loops in order to provide zero delay buffers in the various clock distribution paths. In this approach, the phase lock loop or the delay line loop is used to buffer the clock in such a manner that the clock can be used locally without undergoing any delay. Still another technique employed in the past has been to use phase lock loops or delay line loops having a programmable delay output. In this approach, the system clock is provided as an input to the phase lock loop or the delay line loop, and the output of the clock buffer is a phase shifted version of the input system clock. The amount of the phase shift provided by the loop is programmed by the user so that any clock delay experience along the path can be pre-compensated.
The above known techniques for variable delay clock compensation all suffer from the disadvantage of requiring an accurate prediction of the amount of delay provided by each clock distribution path. In addition, the solution employing a structured set of design rules introduces a constraint on the circuit layout which is not always compatible with other operational requirements of a synchronous electronic system.